The present invention relates to the fabrication of semiconductor integrated circuits (IC's). More particularly, the present invention relates to improved techniques for etching through an IC layer stack, including the low capacitance dielectric layer, during IC fabrication.
In the manufacturing of certain semiconductor integrated circuits, a low dielectric constant (low-K) material may sometimes be employed as the material in the dielectric layer in order to reduce the capacitance of the devices that are formed and to improve their electrical performance. As in all dielectric layers, there is typically a need to etch vias or trenches through the dielectric layer in order to form metal interconnects therethrough. The invention herein addresses the process of forming a via/trench through the low capacitance dielectric layer.
To facilitate discussion, FIG. 1 illustrates a representative layer stack 100, including a photoresist layer 102, a hard mask layer 104, a low capacitance dielectric layer 106, and an etch stop layer 108. Etch stop layer 108 may represent, for example, an etch stop layer for a dual damascene process and is typically formed of a suitable etch stop material such as TiN, SiN, TEOS, or the like. Low capacitance dielectric layer 106 represents a layer of organic low-K material such as SILK by Dow Chemical, Flare by Allied Signal, BCB by Dow Chemical, Paiylene by Novellus, or the like.
Above low capacitance dielectric layer 106, there is shown disposed a hard mask layer 104, which is typically formed of a material such as SiN, SiON (silicon oxynitride) or TEOS. Hard mask layer 104 represents the masking layer that is employed to etch the via/trench in low capacitance dielectric layer 106. The hard mask layer is employed since photoresist is typically ineffective as a masking material when etching the organic low-K material of low capacitance dielectric layer 106. This is because the photoresist material and the organic low-K material tend to have similar chemical characteristics, tend to require a similar etch chemistry, and/or tend to have a similar etch rate. To pattern the hard mask out of hard mask layer 104, a photoresist layer 102 is provided. Photoresist layer 102 may represent, for example, a layer of deep UV or conventional photoresist material.
In FIG. 2, photoresist layer 102 is patterned using a conventional photoresist patterning process. The patterning of photoresist layer 102 creates an opening 202 through which hard mask layer 104 may be etched in a subsequent hard mask etch process.
In FIG. 3, a hard mask etch process is employed to extend opening 202 through hard mask layer 104. In one example, hard mask layer 104 represents a TEOS layer, and the hard mask etch process may take place in a plasma processing reactor using a suitable TEOS etch chemistry such as Ar/C.sub.4 F.sub.8 /C.sub.2 F.sub.6 /O.sub.2 or a conventional TEOS etchant.
In FIG. 4, the low capacitance dielectric layer 106 is being etched. The etching of low capacitance dielectric layer 106 typically takes place in a plasma processing reactor. In the prior art, low capacitance dielectric layer 106 is typically etched using an oxygen-containing gas (such as O.sub.2, CO, CO.sub.2, or the like). A diluent such as N.sub.2 or Ar is typically added to the etchant gas employed to etch through the low capacitance dielectric material. For reasons which shall be explained shortly hereinafter, a passivating agent such as a fluorocarbon gas is also typically added to the etch chemistry.
As is well known, the oxygen species employed to etch through low capacitance dielectric layer 106 tends to etch isotropically, causing the sidewalls in opening 202 to bow instead of maintaining the desired vertical sidewall profile. FIG. 5 illustrates the bowing sidewall that occurs when the etch is allowed to proceed isotropically through low capacitance dielectric layer 106. The bowing effect is exacerbated if over-etching is required to compensate for etch nonuniformity across the wafer. This bowing effect degrades profile control and causes difficulties in subsequent processing steps (such as metal fill).
To maintain profile control and prevent the aforementioned sidewall bowing problem, the prior art typically employs a passivating agent in addition to the oxygen-containing gas. Typically, the passivating agent is a fluorocarbon such as C.sub.4 F.sub.8, C.sub.2 HF.sub.5, CH.sub.2 F.sub.2, or the like. While the addition of the fluorocarbon passivating agent helps preserve the vertical sidewall profile, it tends to facet first the photoresist and subsequently the hard mask, which in turn enlarges opening 202 as the etch proceeds through low capacitance dielectric layer 106.
To elaborate, the oxygen species that is employed to etch through the low capacitance dielectric layer also attacks the overlying photoresist material in photoresist layer 102. Consequently, the thickness of photoresist layer 102 is reduced as the etch proceeds through low capacitance dielectric layer 106. Because the oxygen species attacks the photoresist material isotropically, the photoresist mask often pulls back in regions 402 and 404 of the via/trench. As the photoresist material is worn away by the oxygen species and the photoresist material is pulled back in regions 402 and 404 of FIG. 4, the TEOS hard mask material of hard mask layer 104 is exposed to the fluorocarbon etchant that is added for passivation purposes. Since fluorocarbon is an etchant of TEOS, the exposed hard mask material in regions 408 and 410 are etched away as time goes on, causing the opening in hard mask layer 104 to enlarge. The enlargement of the opening in hard mask layer 104 in turn enlarges the via/trench to be etched through low capacitance dielectric layer 106. With this enlargement, the critical dimension of the via/trench is destroyed. The result is shown in FIG. 6 wherein the resultant via/trench has a larger cross-section than intended.
The use of a fluorocarbon additive also narrows the process window of the low capacitance dielectric layer etch. If too much fluorocarbon is added to the etch chemistry, the etch rate of the low capacitance dielectric layer will be reduced dramatically, until etch stoppage eventually occurs. If too little fluorocarbon is added, there may be insufficient passivation to maintain the desired vertical sidewall profile.
In view of the foregoing, there are desired improved techniques for etching through the low capacitance dielectric layer while maintaining the profile control and preserving the critical dimension of the resultant via/trench.